Conferences: 2014 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2001 2000
Workshops: 2013 2012 2011 2010 2009 2007 2006 2005 2004 2003 2002 2001 2000
Journals: 2013 2012 2007 2005 2004 2003 2001
Theses & TRs: 2013 2010 2009 2008 2007 2006 2005 2004 2003 2002 2001 2000

Conference Publications

    2014

  1. Revolver: Processor Architecture for Power Efficient Loop Execution [PDF]
    Mitchell Hayenga, Vignyan Reddy, and Mikko H. Lipasti
    In Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture (HPCA 2014), Orlando, FL, Feb. 2014.
  2. Precision-Aware Soft Error Protection for GPUs [PDF]
    David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti
    In Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture (HPCA 2014), Orlando, FL, Feb. 2014.
  3. Atomic SC for Simple In-order Processors [PDF]
    Nominated for best paper award!
    Dibakar Gope and Mikko H. Lipasti
    In Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture (HPCA 2014), Orlando, FL, Feb. 2014.
  4. 2013

  5. Wavelength Stealing: An Opportunistic Approach to Channel Sharing in Multi-chip Photonic Interconnects [PDF]
    Arslan Zulfiqar, Pranay Koka, Herb Schwetman, Mikko Lipasti, Xuezhe Zheng, and Ashok V. Krishnamoorthy
    In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)), Davis, CA, Dec. 2013.
  6. Data Compression for Thermal Mitigation in the Hybrid Memory Cube [PDF]
    Mushfique Khurshid and Mikko Lipasti
    In Proceedings of the 31st IEEE International Conference on Computer Design (ICCD 2013), Asheville, NC, Oct. 2013.
  7. REEL: Reducing Effective Execution Latency of Floating Point Operations [PDF]
    Vignyan Kothinti Naresh, Syed Gilani, Michael Schulte, Nam Sung Kim, and Mikko Lipasti
    In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, Sep. 2013.
  8. Accelerating Atomic Operations on the GPU for Broader Applicability [PDF]
    Sean Franey and Mikko H. Lipasti
    In Proceedings of the 7th IEEE Network on Chip Symposium, Tempe, AZ, April 2013.
  9. Bridging the Semantic Gap: Emulating Biological Neuronal Behaviors with Simple Digital Neurons [PDF]
    Andrew Nere, Atif Hashmi, Mikko Lipasti, and Giulio Tononi
    In Proceedings of the 19th IEEE International Symposium on High-Performance Computer Architecture (HPCA-19), Shenzhen, China, February 2013.
  10. 2012

  11. BenchNN: On the Broad Potential Application Scope of Hardware Neural Network Accelerators [PDF]
    Nominated for best paper award!
    Tianshi Chen, Yunji Chen, Marc Duranton, Qi Guo, Atif Hashmi, Mikko Lipasti, Andrew Nere, Shi Qiu, Michele Sebag, Olivier Temam
    In Proceedings of the 2012 IEEE International Symposium on Workload Characterization (IISWC 2012), San Diego, CA, Nov 2012.
  12. Mitigating Random Variation with Spare RIBs: Redundant Intermediate Bitslices [PDF]
    David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti
    In Proceedings of the 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), Boston, MA, June 2012.
  13. 2011

  14. CRAM: Coded Registers for Amplified Multiporting [PDF]
    Vignyan Reddy Kothinti Naresh, David J. Palframan, and Mikko H. Lipasti
    In Proceedings of the 44th International Symposium on Microarchitecture (MICRO-44), Porto Alegre, Brazil, December 2011.
  15. The NoX Router [PDF][Slides]
    Nominated for best paper award!
    Mitchell Hayenga and Mikko H. Lipasti
    In Proceedings of the 44th International Symposium on Microarchitecture (MICRO-44), Porto Alegre, Brazil, December 2011.
  16. Automatic Abstraction and Fault Tolerance in Cortical Microarchitectures[PDF]
    Atif Hashmi, Hugues Berry, Olivier Temam, and Mikko H. Lipasti
    In Proceedings of the 38th International Symposium on Computer Architecture (ISCA-38), San Jose, CA, June 2011
  17. CRIB: Consolidated Rename, Issue, and Bypass[PDF]
    Erika Gunadi and Mikko H. Lipasti
    In Proceedings of the 38th International Symposium on Computer Architecture (ISCA-38), San Jose, CA, June 2011
  18. Profiling Heterogeneous Multi-GPU Systems to Accelerate Cortically Inspired Learning Algorithms[PDF]
    Selected as best paper in track!
    Andrew Nere, Atif Hashmi, and Mikko H. Lipasti
    In Proceedings of the 25th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2011), Anchorage, Alaska, May 2011.
  19. Learning through Spatially Localized and Temporally Correlated Spontaneous Activations [PDF]
    Atif Hashmi, Andrew Nere, and Mikko H. Lipasti
    In Proceedings of the 15th International Conference on Cognitive and Neural Systems (ICCNS-15), Boston, MA, May 2011 (abstract and talk).
  20. Accelerating Search and Recognition Workloads with SSE 4.2 String and Text Processing Instructions[PDF]
    Guangyu Shi, Min Li, and Mikko H. Lipasti
    In Proceedings of the 2011 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2011), Austin, TX, April 2011.
  21. Time Redundant Parity for Low-Cost Transient Error Detection[PDF]
    David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti
    In Proceedings of Design, Automation, and Test in Europe (DATE 2011), Grenoble, France, March 2011.
  22. A Case for Neuromorphic Instruction Set Architectures[PDF]
    Atif Hashmi, Andrew Nere, James Thomas, and Mikko H. Lipasti
    In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Newport Beach, CA, March 2011.
  23. Atomic Coherence: Leveraging Nanophotonics to Build Race-Free Cache Coherence Protocols[PDF]
    Dana Vantrease, Nate Binkert, and Mikko H. Lipasti
    In Proceedings of the 17th IEEE International Symposium on High-Performance Computer Architecture (HPCA-17), San Antonio, TX, February 2010.
  24. 2010

  25. Combating Aging with the Colt Duty Cycle Equalizer [PDF]
    Erika Gunadi, Abhisek Sinkar, Nam Sung Kim, and Mikko Lipasti
    In Proceedings of the 43rd International Symposium on Microarchitecture (MICRO-43), Atlanta, GA, December 2010.
  26. Discovering Cortical Algorithms [PDF]
    Atif Hashmi and Mikko Lipasti
    In Proceedings of the International Conference on Neural Computation (ICNC), Valencia, Spain, October 2010.
  27. Discovering Cortical Algorithms [PDF]
    Atif Hashmi and Mikko Lipasti
    In Proceedings of the 14th International Conference on Cognitive and Neural Systems (ICCNS-14), Boston, MA, May 2010 (abstract and talk).
  28. 2009

  29. Light Speed Arbitration and Flow Control for Nanophotonic Interconnects [PDF]
    Dana Vantrease , Nathan Binkert, Robert Schreiber, and Mikko Lipasti
    In Proceedings of the 42nd International Symposium on Microarchitecture (MICRO-42), New York, NY, December 2009.
  30. SCARAB: A Single Cycle Adaptive Routing and Bufferless Network [PDF](revised)
    Mitchell Hayenga, Natalie Enright Jerger, Mikko Lipasti
    In Proceedings of the 42nd International Symposium on Microarchitecture (MICRO-42), New York, NY, December 2009.
  31. Achieving Predictable Performance Through Better Memory Controller Placement in Many-Core CMPs [PDF]
    Dennis Abts, Natalie Enright Jerger, John Kim, Dan Gibson, Mikko Lipasti
    In Proceedings of the 36th Annual International Symposium on Computer Architecture, Austin, TX, June 2009.
  32. Cortical Columns: Building Blocks for Intelligent Systems [PDF]
    Atif Hashmi and Mikko Lipasti
    In Proceedings of IEEE Symposium on Computational Intelligence for Multimedia Signal and Vision Processing, Nashville, TN, March 2009.
  33. 2008

  34. Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence [PDF]
    Natalie Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti
    In Proceedings of the International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, November 2008.
  35. Skewed Redundancy [PDF]
    Gordon B. Bell and Mikko H. Lipasti
    In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT-17), October, 2008.
  36. Accelerating Search and Recognition with a TCAM Functional Unit [PDF]
    Atif Hashmi and Mikko H. Lipasti
    In Proceedings of the International Conference on Computer Design (ICCD), October, 2008.
  37. An Accurate Flip-flop Selection Technique for Reducing Logic SER [PDF]
    Eric L. Hill, Mikko H. Lipasti, and Kewal K. Saluja
    In Proceedings of The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-2008), Anchorage, Alaska, June 2008.
  38. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support [PDF]
    Natalie Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti
    In Proceedings of the International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008.
  39. Circuit-Switched Coherence [PDF]
    Natalie Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti
    In Proceedings of the IEEE Network on Chip Symposium, Newcastle-Upon-Tyne, UK, April 2008.
  40. Power-Aware DRAM Speculation [PDF]
    Nidhi Aggarwal, Jason Cantin, Mikko H. Lipasti, and James E. Smith
    In Proceedings of 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, February 2008.
  41. 2007

  42. Transparent Mode Flip-Flops for Collapsible Pipelines [PDF]
    Eric Hill and Mikko H. Lipasti
    In Proceedings of the 25th IEEE International Conference on Computer Design (ICCD-25), Lake Tahoe, CA, October 2007
  43. A Position-Insensitive Finished Store Buffer [PDF]
    Erika Gunadi and Mikko H. Lipasti
    In Proceedings of the 25th International Symposium on Computer Design (ICCD-25), Lake Tahoe, CA, October 2007. Slides available
  44. An Evaluation of Server Consolidation Workloads for Multi-core Designs [PDF]
    Natalie Enright Jerger, Dana Vantrease, and Mikko H. Lipasti
    In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Boston, MA, September 2007.
  45. Power-Aware Operand Delivery [PDF]
    Erika Gunadi and Mikko H. Lipasti
    In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED) , Portland, OR, August 2007. Poster available
  46. Speculative Optimization Using Hardware-Monitored Guarded Regions for Java Virtual Machines [PDF]
    Lixin Su and Mikko H. Lipasti
    In Proceedings of of the 3rd International ACM SIGPLAN/SIGOPS Conference on Virtual Execution Environments (VEE-3), San Diego, CA, June 2007.
  47. 2006

  48. Stall Cycle Redistribution in a Transparent Fetch Pipeline [PDF]
    Eric Hill and Mikko H. Lipasti
    In Proceedings of Intl. Symposium on Low Power Electronics and Design, October 2006.
  49. Stealth Prefetching [PDF]
    Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
    In Proceedings of: 12th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), October 2006.
  50. Dynamic Class Hierarchy Mutation [PDF]
    Lixin Su and Mikko H. Lipasti
    In Proceedings of of the 4th International Symposium on Code Generation and Optimization (CGO-4), New York, NY, March 2006.
  51. Friendly Fire: Understanding the Effects of Multiprocessor Prefetching [PDF]
    Natalie Enright Jerger, Eric L Hill, and Mikko H. Lipasti
    In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006.
  52. An Approach for Implementing Efficient Superscalar CISC Processors [PDF]
    Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, and James E. Smith
    In Proceedings of of the 12th International Symposium on High-Performance Computer Architecture (HPCA-12), Austin, TX, February 2006.
  53. 2005

  54. Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking [PDF]
    Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
    In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA-32), Madison, WI, June 2005.
  55. Reaping the Benefit of Temporal Silence to Improve Communication Performance [PDF]
    Kevin M. Lepak and Mikko H. Lipasti
    In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005), Austin, TX, March 2005.
  56. 2004

  57. Memory Ordering: A Value-based Approach [PDF][PS][.bib]
    Harold W. Cain and Mikko H. Lipasti
    In Proceedings of the 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004. Slides available
  58. Physical Register Inlining [PDF][PS]
    Mikko H. Lipasti, Brian R. Mestan, and Erika Gunadi
    In Proceedings of the 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004. Slides available
  59. Deconstructing Commit [PDF][PS][.bib]
    Gordon B. Bell and Mikko H. Lipasti
    In Proceedings of the 4th International Symposium on Performance Analysis of Systems and Software (ISPASS-4), Austin, TX, March 2004. [Slides to be available]
  60. Understanding Scheduling Replay Schemes [PDF][PS][.bib]
    Ilhyun Kim and Mikko H. Lipasti
    In Proceedings of the 10th International Symposium on High-performance Computer Architecture (HPCA-10), Madrid, Spain, February 2004. [Slides to be available]
  61. 2003

  62. Macro-op Scheduling: Relaxing Scheduling Loop Constraints [PDF][PS][.bib]
    Ilhyun Kim and Mikko H. Lipasti
    In Proceedings of the 36th International Symposium on Microarchitecture (MICRO-36), San Diego, CA, December 2003. Slides available
  63. Redeeming IPC as a Performance Metric for Multithreaded Programs [pdf, ps]
    Kevin M. Lepak, Harold W. Cain, and Mikko H. Lipasti
    In Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, September, 2003.

  64. Constraint Graph Analysis of Multithreaded Programs [pdf, ps]
    Harold W. Cain, Mikko H. Lipasti, and Ravi Nair
    In Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, September, 2003.

  65. Exploiting Partial Operand Knowledge [pdf, ps]
    Brian Mestan and Mikko H. Lipasti
    In Proceedings of the International Conference on Parallel Processing (ICPP-03), October, 2003.

  66. Half-Price Architecture [PDF][PS][.bib]
    Ilhyun Kim and Mikko H. Lipasti
    In Proceedings of the 30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003. Slides available pp
  67. 2002

  68. A Case for Vector Network Processors [PDF]
    Madhusudanan Seshadri and Mikko H. Lipasti
    In Proceedings of Network Processor Conference West, San Jose, CA, October 2002.
  69. Temporally Silent Stores [PDF][PS][.bib]
    Kevin M. Lepak and Mikko H. Lipasti
    In Proceedings of 10th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002. Slides available
  70. Verifying Sequential Consistency Using Vector Clocks [PDF][PS][.bib]
    Harold W. Cain and Mikko H. Lipasti
    In Proceedings of the 14th Symposium on Parallel Algorithms and Architectures Revue , August 2002. Slides to be available
  71. Avoiding Initialization Misses to the Heap [PDF][PS][.bib]
    Jarrod A. Lewis, Bryan Black, and Mikko H. Lipasti
    In Proceedings of 29th International Symposium on Computer Architecture (ISCA-29), May 2002. Slides available
  72. Implementing Optimizations at Decode Time [PDF][PS][.bib]
    Ilhyun Kim and Mikko H. Lipasti
    In Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002. Slides available
  73. 2001

  74. Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing [PDF][PS][.bib]
    Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti
    In Proceedings of the 34th International Symposium on Microarchitecture, December 2001. Slides available
  75. An Architectural Evaluation of Java TPC-W [PDF][PS][.bib]
    Harold W. Cain, Ravi Rajwar, Morris Marden and Mikko H. Lipasti
    In Proceedings of The Seventh International Symposium on High-Performance Computer Architecture, January 2001. Slides available
  76. 2000

  77. Silent Stores for Free [PDF][PS][.bib]
    Kevin M. Lepak and Mikko H. Lipasti
    In Proceedings of The 33rd Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-33), December, 2000. Slides available
  78. Characterization of Silent Stores[PDF][PS][.bib]
    Gordon B. Bell, Kevin M. Lepak, and Mikko H. Lipasti
    International Conference on Parallel Architectures and Compilation Techniques, October, 2000. Slides available
  79. On the Value Locality of Store Instructions[PDF][PS][.bib]
    Kevin M. Lepak and Mikko H. Lipasti
    In Proceedings of the 27th International Symposium on Computer Architecture, June, 2000. Slides available Trip pictures

Workshop Publications

    2013

  1. Online and Operand-Aware Detection of Failures by Utilizing False Alarm Vectors [PDF]
    Amir Yazdanbakhsh, David Palframan, Azadeh Davoodi, Nam Sung Kim, and Mikko Lipasti
    In Proceeedings of 22nd International Workshop on Logic & Synthesis (IWLS), Austin, TX, June 2013.
  2. 2012

  3. Analyzing the Soft Error Resilience of the CRIB Microarchitecture [PDF]
    Vignyan Reddy Kothinti Naresh, David J. Palframan and Mikko H. Lipasti
    In Proceedings of the 3rd Workshop on Resilient Architectures (WRA-3), Vancouver, BC, December 2012.
  4. Edge Chasing Delayed Consistency: Pushing the Limits of Weak Memory Models [PDF]
    Harold W. Cain and Mikko H. Lipasti
    In Proceedings of the Workshop on Relaxing Synchronization for Multicore and Manycore Scalability (RACES'12), Tucson, AZ, October 2012 (archival publication via ACM Digital Library).
  5. Pitfalls of Orion-based Simulation [PDF]
    Mitchell Hayenga, Daniel Johnson, Mikko Lipasti
    In Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking (WDDD-12), Portland, OR, June 2012.
  6. 2011

  7. Spare RIBs: Redundant Intermediate Bitslices [PDF]
    David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti
    In Proceedings of the 2nd Workshop on Resilient Architectures (WRA-2), Porto Alegre, Brazil, December 2011.
  8. Perceptron Branch Prediction with Separated Taken/Not-Taken Weight Tables [PDF]
    Guangyu Shi and Mikko H. Lipasti
    In Proceedings of the 2nd JILP Workshop on Computer Architecture Competitions: Championship Branch Prediction (JWAC-2), San Jose, CA, June 2011.
  9. 2010

  10. MadCache: A PC-aware Cache Insertion Policy [PDF]
    Mitchell Hayenga, Andrew T. Nere and Mikko H. Lipasti
    In Proceedings of the 1st JILP Workshop on Computer Architecture Competitons(JWAC-1),Saint-Malo, France June 2010.
  11. Logic Soft Errors in a Parallel CISC Decoder [PDF]
    Eric L. Hill and Mikko H. Lipasti
    In Proceedings of the 2010 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 2010), Stanford University, CA, March, 2010.
  12. The Effect of Pipeline Depth on Logic Soft Errors [PDF]
    Eric L. Hill and Mikko H. Lipasti
    In Proceedings of the 2010 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 2010), Stanford University, CA, March, 2010.
  13. Cortical Architectures on a GPGPU [PDF]
    Andrew T. Nere and Mikko H. Lipasti
    In Proceedings of the Workshop on General-Purpose Computation on Graphics Processing Units, Pittsburgh, PA, March, 2010.
  14. 2009

  15. Leveraging Progress in Neurobiology for Computing Systems [PDF]
    Atif Hashmi, Hugues Berry, Olivier Temam and Mikko H. Lipasti
    Workshop on New Directions in Computer Architecturem held in Conjunction with 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), New York, NY, December, 2009.
  16. Nanophotonic Barriers [PDF]
    Nathan Binkert, Al Davis, Mikko H. Lipasti, Robert Schreiber, and Dana Vantrease
    Workshop on Photonic Interconnects And Computer Architecture. Held in Conjunction with 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), New York, NY, December, 2009.
  17. 2007

  18. Achieving Fault Detection & Performance on CMPs [PDF]
    Gordon B. Bell and Mikko H. Lipasti
    In Proceedings of the SELSE 3 Workshop - Silicon Errors in Logic - System Effects, Austin, TX, March, 2007.
  19. 2006

  20. Phase-based Adaptive Branch Predictor: Seeing the Forest for the Trees [PDF]
    Karthik Jayaraman, Vivek Shrivastava, Brian Pellin, Martin Hock, and Mikko H. Lipasti
    Workshop on Introspective Architecture, Austin, TX, February, 2006.
  21. 2005

  22. Opportunities for Cache Friendly Process Scheduling [PDF]
    Pranay Koka and Mikko H. Lipasti
    Workshop on Interaction between Operating System and Computer Architecture, October, 2005. Slides available
  23. A Comparison of SPECjAppServer2002 and SPECjAppServer2004 [PDF]
    Lixin Su, Kingsum Chow, Kumar Shiv, and Ashish Jha
    Workshop on Computer Architecture Evaluation using Commercial Workloads, in conjunction with HPCA, February, 2005.
  24. 2004

  25. Cache Pipelining with Partial Operand Knowledge [PDF]
    Erika Gunadi and Mikko H. Lipasti
    Workshop on Complexity-Effective Design, in conjunction with ISCA, June, 2004. Slides available
  26. Characterization of an IMAP Server on a Shared-Memory Multiprocessor [PDF] [PS]
    Pranay Koka and Mikko H. Lipasti
    Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads , in conjunction with HPCA, February, 2004.
  27. 2003

  28. Exploring Efficient SMT Branch Predictor Design [PDF] [PS]
    Matt Ramsay, Chris Feucht, and Mikko H. Lipasti
    Workshop on Complexity-Effective Design, in conjunction with ISCA, June, 2003.
  29. 2002

  30. Precise and Accurate Processor Simulation [PDF] [PS]
    Harold W. Cain, Kevin M. Lepak, Brandon A. Schwartz, and Mikko H. Lipasti
    Workshop on Computer Architecture Evaluation using Commercial Workloads, in conjunction with HPCA, February, 2002.
  31. Comparison of Memory System Behavior in Java and Non-Java Commercial Workloads [PDF] [PS]
    Morris Marden, Shih-Lien Lu, Konrad Lai, and Mikko Lipasti
    Workshop on Computer Architecture Evaluation using Commercial Workloads, in conjunction with HPCA, February, 2002.
  32. 2001

  33. Dynamic Verification of Cache Coherence Protocols [PDF] [PS]
    Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
    Workshop on Memory Performance Issues, in conjunction with ISCA, June, 2001. Slides available
  34. Power Efficient Cache Coherence [PDF] [PS]
    Craig Saldanha and Mikko H. Lipasti
    Workshop on Memory Performance Issues, in conjunction with ISCA, June, 2001. Slides available
  35. 2000

  36. A Dynamic Binary Translation Approach to Architectural Simulation [PDF] [PS]
    Harold W. Cain, Kevin M. Lepak and Mikko H. Lipasti
    Workshop on Binary Translation(WBT-2000), in conjunction with PACT, October, 2000. Slides available
  37. Also appearing in Computer Architecture News, Vol. 29, No. 1, March 2001.

Journal Articles and Book Chapters

    2013

  1. Resilient High-Performance Processors with Spare RIBs [PDF]
    David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti
    IEEE MICRO, vol. 33, no. 4, July-Aug 2013 (special issue on reliability).
  2. 2012

  3. Simulating Cortical Networks on Heterogeneous Multi-GPU Systems [PDF]
    Andrew Nere, Sean Franey, Atif Hashmi, and Mikko Lipasti
    Journal of Parallel and Distributed Computing, to appear, 2012.
  4. A Cortically-Inspired Learning Model [PDF]
    Atif Hashmi and Mikko Lipasti
    Studies in Computational Intelligence, Vol. 399, 2012 (Special Issue).
  5. 2007

  6. Narrow Width Dynamic Scheduling [PDF]
    Erika Gunadi and Mikko H. Lipasti
    Journal of Instruction-Level Parallelism, Vol. 9, April 2007 (http://www.jilp.org/vol9).
  7. Circuit-Switched Coherence [IEEE Xplorer][PDF]
    Natalie Enright Jerger, Mikko Lipasti, and Li-Shiuan Peh
    IEEE Computer Architecture Letters, vol. 6, no. 1, Jan-Jun, 2007.
  8. 2005

  9. Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays [IEEE Xplorer][PDF]
    Jason Cantin, Mikko H. Lipasti, James E. Smith, Andreas Moshovos, and Babak Falsafi
    IEEE Micro, Vol. 26, no. 1 (Special Issue on Top Picks in Computer Architecture), pp. 70-79.
  10. The Complexity of Verifying Memory Coherence and Consistency [IEEE Xplore][PDF]
    J. F. Cantin, M. H. Lipasti, and J. E. Smith
    IEEE Transactions on Parallel and Distributed Systems, Vol. 16, No. 7, July 2005.
  11. 2004

  12. Memory ordering: a value-based Approach [IEEE Xplore] [PDF]
    Harold W. Cain and Mikko H. Lipasti
    IEEE Micro, vol.24, no.6, pp. 110- 117, Nov.-Dec. 2004 (Special Issue on Top Picks in Computer Architecture).
  13. 2003

  14. Power Efficient Cache Coherence [PDF as published][PS as published]
    Full-length technical report version [PDF full-length][PS full-length]
    Craig Saldanha and Mikko H. Lipasti
    High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003.
  15. Dynamic Verification of Cache Coherence Protocols
    Jason F. Cantin, Mikko H. Lipasti, and James E. Smith
    High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003.

    2001

  16. Silent Stores and Store Value Locality[PDF][PS][.bib]
    Kevin M. Lepak, Gordon B. Bell, and Mikko H. Lipasti
    IEEE Transactions on Computers, Vol. 50, No. 11, November 2001

Theses and Technical Reports

    2013

  1. Computing with Hierarchical Attractors of Spiking Neurons [PDF]
    Andrew Nere, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.d. degree in ECE, May 2013
  2. Power-Efficient Loop Execution Techniques [PDF]
    Mitchell Hayenga, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.d. degree in ECE, Aug 2013
  3. 2010

  4. CRIB: Consolidated Rename, Issue, and Bypass [PDF]
    Erika Gunadi, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.d. degree in ECE, May 2010
  5. 2009

    2008

  6. Chip Multiprocessor Coherence and Interconnect System Design [PDF]
    Natalie Enright Jerger, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.d. degree in ECE, December 2008
  7. 2007

  8. Latency- and Error-Tolerant Redundant Execution [PDF]
    Gordon B Bell, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.D. degree in ECE, December 2007
  9. 2006

  10. Profligate Execution[PDF]
    Gordon B. Bell and Mikko H. Lipasti
    Technical Report, September 2006
  11. 2005

  12. Dynamic Scheduling with Narrow Operand Values[PDF][PS]
    Erika Gunadi
    Submitted in partial fulfillment of the M.S. degree in ECE, June 2005
  13. 2004

  14. Detecting and Exploiting Causal Relationships in Hardware Shared-Memory Multiprocessors [PDF]
    Harold W Cain
    Submitted in partial fulfillment of the Ph.D. degree in CS, Dec 2004
  15. Benefits of Value-Range Cache: A Limit Study [PDF][PS]
    Ramya K Narayana
    Submitted in partial fulfillment of the M.S. degree in ECE, May 2004
  16. Macro-op Scheduling and Execution [PDF]
    Ilhyun Kim, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.D. degree in ECE, May 2004
  17. 2003

  18. Exploring, Defining, and Exploiting Recent Store Value Locality [PDF]
    Kevin M Lepak, Ph.D. Thesis
    Submitted in partial fulfillment of the Ph.D. degree in ECE, December 2003
  19. Dataflow Dominance: A Definition and Characterization [PDF][PS]
    Matt Ramsay
    Submitted in partial fulfillment of the M.S. degree in ECE, December 2003
  20. 2002

  21. Exploiting Partial Operand Knowledge [PDF][PS]
    Brian Mestan
    Submitted in partial fulfillment of the M.S. degree in ECE, May, 2002
  22. Vector Network Processors [PDF][PS]
    Madhusudanan Seshadri
    Submitted in partial fulfillment of the M.S. degree in ECE, May, 2002
  23. 2001

  24. Characterization of Silent Stores [PDF][PS]
    Gordon Bell
    Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
  25. A Genetic Algorithm for Designing Parallel Processor Interconnection Networks [PDF][PS]
    Morris Marden
    Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
  26. Performance and Power via Speculative Decode [PDF][PS]
    Ilhyun Kim
    Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
  27. Power Efficient Cache Coherence
    Craig Saldanha
    Submitted in partial fulfillment of the M.S. degree in ECE, May 18, 2001
  28. 2000

  29. Silent Stores for Free: Reducing the Cost of Store Verification [PDF][PS]
    Kevin M. Lepak
    Submitted in partial fulfillment of the M.S. degree in ECE, December 15, 2000


Last Updated: Feb-16-2014 22:02:32 CST