Workshop on Duplicating, Deconstructing and Debunking

May 26, 2002
Anchorage, Alaska

Organized by:

Bryan Black, Intel Labs, bryan.black@intel.com

Mikko Lipasti, University of Wisconsin, mikko@engr.wisc.edu

Final Program

Session 1: Multiple Threads or Processors
Evaluation of Snoop-Energy Reduction Techniques for Chip-Multiprocessors
Magnus Ekman, Fredrik Dahlgren, Per Stenström
Chalmers University of Technology and Ericsson Mobile Platforms
STiNG Revisited: Performance of Commercial Database Benchmarks on a CC-NUMA Computer System
Russell Clapp, Don DeSota, Carl Love, and Adrian Moga
IBM
Performance Analysis of Simultaneous Multithreading in a PowerPC-based Processor
F.N. Eskesen, M. Hack, T. Kimbrel, M.S. Squillante, R.J. Eickemeyer, S.R. Kunkel
IBM
Session 2: Caches and Branch Predictors
Evaluation of the Performance of Polynomial Set Index Functions
Hans Vandierendonck and Koen De Bosschere
Ghent University
The Benefit of Multiple Branch Prediction on Dynamically Scheduled Systems
David M. Koppelman
Louisiana State University
Demystifying Intel Branch Predictors
Milena Milenkovic, Aleksandar Milenkovic, and Jeffrey Kulick
University of Alabama in Huntsville
Session 3: ILP Techniques
Revisiting Instruction Level Reuse
Daniel Citron and Dror G. Feitelson
IBM and The Hebrew University of Jerusalem
Memory Bypassing: Not Worth the Effort
Gabriel H. Loh, Rahul Sami, and Daniel H. Friendly
Yale University