BitSAD Domain-specific compiler for Bitstream Applications

Developing and deploying algorithmic kernels and end-to-end applications using stochastic logic has proven to be an extremely challenging, time-consuming, and error-prone process, which discourages designers from adopting this approach. In our experience with developing bitstream-based linear solvers, algorithms are first developed in Matlab using floating-point data types, then rewritten to emulate stochastic logic in a high-level simulator, and finally prototyped using Verilog RTL on an FPGA substrate. Implementation and validation of three separate realizations is error-prone and requires significant duplication of effort.

To address this challenge, we have developed BitSAD, the first domain-specific language for bitstream computing. BitSAD allows users to write high-level algorithms like an iterative SVD in a Matlab-like syntax, utilizing high-level programming language features, custom data types for bitstream computing and libraries to perform convenient linear algebra matrix operations. Any algorithm developed in BitSAD can be simulated at the software-level to debug bitstream-level issues quickly, and the code automatically generates synthesizable Verilog that implements the algorithm. The Verilog can then be effortlessly deployed on a field-programmable gate array (FPGA) or even synthesized into a custom chip. In order to facilitate widespread adoption of this language, we have released the BitSAD compiler under an open source license.

BitBench Benchmark Suite for Bitstream Computing

The stochastic computing research community has struggled with standardized ways of evaluating and comparing stochastic computing implementations. To address this challenge, we developed BitBench, the first standardized benchmark suite for bitstream computing. BitBench includes six key numeric kernels and two end-to-end applications, along with representative input data sets and run rules, and enables a standardized approach for benchmarking stochastic computing implementations. Like BitSAD, BitBench has been released under an open source license and can be downloaded from https://github.com/UW-PHARM/BitBench.

Java TPC-W Implementation Distribution

In an attempt to encourage widespread use of realistic, modern application benchmarks in computer systems research, we are making our implementation of the TPC-W benchmark publicly available. This implementation is based on the TPC-W specification version 1.0.1. It strays from the official benchmark specification in a few minor areas, which are specified in documentation included with the distribution. Credit for this implementation goes to the students of Prof. Lipasti's Fall 1999 ECE 902 course, where most of this work took place.

This implementation is completely written in the Java programming language, making use of the Java Servlet API and the JDBC API for database connectivity. Running this benchmark requires the use of a servlet-capable web server as well as a relational database system. We have tested this implementation with the IBM WebSphere , Apache/JServ, Sun Java Web Server, and Jigsaw Web Servers, as well as the IBM DB2 relational database system.

Amit Manjhi at CMU has adapted this implementation of TPC-W to run with Tomcat and Mysql. Check here for more information.

Christian Plattner has adapted this implementation of TPC-W to run with Postgresql. Check http://www.inf.ethz.ch/~cplattne/work/tpcw-postgresql.html for more information. NOTE: This link to ETHZ no longer works, so I took the liberty of creating a local copy of the document from web.archive.org: click here to read it.

Jan Kiefer has created an installer for this software, available from http://tpcw.deadpixel.de>.

Download a copy of the TPC-W Java source code (~700 KB gzipped tar file).
[No longer up]Browse the TPC-W bookstore website implemented by our Java servlet code (for best results, turn off cookies in your browser).

Architectural Characterization

We are also performing a detailed microarchitectural characterization of this workload. Preliminary results of our ongoing work were presented at the 3rd Workshop On Computer Architecture Evaluation Using Commercial Workloads (CAECW) at the January 2000 HPCA conference in Toulouse, France.

Here are the presentation slides.

Disclaimer:

Any information presented here is not in any sense based on the official TPC-W benchmark, and is not comparable to an official TPC result. Due to the TPC fair use policy, no-one should construe the results presented or comments made as having anything to do with the official TPC-W benchmark or any other TPC benchmark for that matter.

CAECW Talk Title

Characterizing a Java Implementation of TPC-W

Authors

Todd Bezenek, Trey Cain, Ross Dickson, Timothy Heil, Milo Martin, Collin McCurdy, Ravi Rajwar, Eric Weglarz, Craig Zilles, and Mikko Lipasti

Affiliation

Department of Electrical and Computer Engineering and Computer Sciences Department, University of Wisconsin - Madison

Talk Abstract

The Transaction Processing Performance Council (TPC) is in the process of developing a new benchmark, TPC-W, that attempts to model the application behavior of online web merchant sites. TPC-W consists of a web serving component that models online browsing and purchasing, as well as an on-line transaction processing (OLTP) component that models order processing and tracking. We implement this benchmark based on the preliminary specification that TPC has made available for public review. The remote browser emulation, web merchant application logic, and web server of our version of TPC-W are implemented completely in Java, using the Jigsaw Web Server, the servlet interface for dynamic html and forms processing, and relational database connectivity through the standard JDBC (Java Database Connectivity) interface. The OLTP component is implemented using the IBM DB2 relational database management system.

We characterize our implementation of TPC-W by running it under a full-system simulation environment in a single-tier configuration. Work is in progress to bring up our TPC-W implementation under two different instruction sets (PowerPC and SPARC) running under their respective full-system simulators (SimOS-PPC and SimICS). We will discuss the challenges we faced in bringing up a complex, networked, multitier workload implemented in a new language (Java) on a full system simulator. We will also present preliminary data characterizing the instruction stream, branch predictability, cache behavior, and multiprocessor data sharing patterns of this new workload.

Go back to Mikko's home page.
Go to the PHARM group page.

Last Updated: Apr-12-2024 10:59:11 CDT