[ CASES17, ISCA17a, ISCA17b, CAL16, ICCD16, ISCA15, GLSVLSI15, HPCA15A, HPCA15B, MICRO14, CAL14, ISLPED14, CBP14, HPCA14A, HPCA14B, HPCA14C, ICCD13, ISLPED13, IWLS13, WRA12, DSN12, MICRO11, WRA11, JWAC11, ISCA11, DATE11, MICRO10, SELSE10a, SELSE10b, PACT08, DSN08, ICCD07a, ICCD07b, SELSE07, ISLPED06 ]
Computer architects face broad new challenges in the twilight years of CMOS: while device density will continue to increase, device reliability, process variability, thermal, power delivery, and energy supply constraints will severely complicate any effort to extract additional performance and functionality from an abundant supply of on-chip transistors. This projects is focused on finding new ways to address these technology-related challenges by rethinking and restructuring conventional circuit, logic, and microarchitectural approaches to better suit the constraints of future CMOS technology.
The amazing computational abilities of the human neocortex are evident to everyone, yet their algorithmic underpinnings are surprisingly poorly understood by the scientific community. The two goals of this project are to (1) improve scientific understanding of cortical structures and algorithms, and (2) build future computing systems that employ similar, cortically-inspired mechanisms. We believe that such systems will be especially well-suited to future nanoscale technologies, since cortical algorithms are inherently tolerant of faults and variations.
As we move into the era of many-core processor chips, the area, power, and performance overheads of the on-chip interconnect becomes more and more important. We are actively investigating both electrical and optical networks along with co-designed cache coherence protocols for reducing these overheads in chips with sixteen or more cores per die.
Relevant and appropriate workloads are arguably the most important input to any research work in computer architecture. Our group continues to characterize, develop, and create new workloads as well as novel architectural approaches that exploit key attributes of such workloads.